LogiCORE IP FIFO Generator v8.3 Data Sheet (AXI) - 8.3 English - The Xilinx LogiCORE IP FIFO Generator is a fully verified first-in first-out (FIFO) memory queue for applications requiring in-order storage and retrieval. The core provides an optimized solution for all FIFO configurations and delivers maximum performance (up to 500 MHz) while utilizing minimum resources. This document contains information about the AXI4 version of the core. - DS317
fifo_generator_ds317.pdf
- Document ID
- DS317
- Release Date
- 2011-10-19
- Version
- 8.3 English