LogiCORE IP JESD204 v5.1 Product Brief (AXI) - 5.1 English - The LogiCORE IP JESD204 core implements a JESD204B interface supporting line rates from 1 Gb/s to 12.5 Gb/s on 1 to 8 lanes using GTX or GTP transceivers in Zynq-7000 AP SoC devices and series-7 FPGAs. The JESD204 core can be configured as transmit or receive. In addition, an example design is provided in Verilog. - PB011

Document ID

PB011

Release Date

2013-12-18

Version

5.1 English