LogiCORE IP JESD204 v3.1 Product Brief (AXI) - 3.1 English - The LogiCORE IP JESD204 core implements a JESD204A or JESD204B interface supporting line rates of 1, 2.5, 3.125 and 6.25 Gb/s on 1, 2 or 4 lanes using GTX transceivers in Virtex-6 and Kintex-7 FPGAs. The JESD204 core can be configured as Transmit or Receive. The JESD204 core is a fully-verified solution design delivered via the Xilinx Core Generator software as an NGC netlist. In addition, an example design is provided in Verilog.