Vivado Design Suite User Guide: Design Analysis and Closure Techniques - 2019.2 English - Details features of the Vivado® tools for logic and timing analysis of an FPGA design, with reports and messages generated by the tools. Discusses methods for reaching timing closure, including reviewing clock trees and timing constraints, design floorplanning, and balancing runtime with results. - UG906
ug906-vivado-design-analysis.pdf
- Document ID
- UG906
- Release Date
- 2020-06-10
- Version
- 2019.2 English