Vivado Design Suite User Guide: Using Constraints - 2017.3 English - Describes using Xilinx® Design Constraints (XDC) in Vivado® tools. XDC combines industry-standard Synopsys Design Constraints (SDC) and Xilinx proprietary constraints. Details creating XDC to define clocks, I/O delays, and timing exceptions like false and multicycle paths, and min/max delays. - UG903
ug903-vivado-using-constraints.pdf
- Document ID
- UG903
- Release Date
- 2017-10-04
- Version
- 2017.3 English