Vivado Design Suite Tutorial: Logic Simulation - 2017.2 English - Introduces the Vivado® simulator to interactively simulate and debug Xilinx® FPGA designs in the Vivado Integrated Design Environment (IDE). The Vivado simulator is an HDL simulator that lets you perform behavioral, functional, and timing simulations for VHDL, Verilog, and mixed-language designs. - UG937
ug937-vivado-design-suite-simulation-tutorial.pdf
- Document_ID
- UG937
- Release_Date
- 2017-06-07
- Version
- 2017.2 English