Vivado Design Suite Tutorial: Programming and Debugging - 2017.2 English - Describes debugging Xilinx® FPGA designs using the Integrated Logic Analyzer (ILA) core in the Vivado® Design Suite and the Vivado logic analyzer to debug com problems in FPGA logic designs. Uses the Vivado logic analyzer in real-time and a KC705 Evaluation Board featuring a Kintex®-7 device. - UG936
ug936-vivado-tutorial-programming-debugging.pdf
- Document ID
- UG936
- Release Date
- 2017-06-07
- Version
- 2017.2 English