Vivado Design Suite Tutorial: I/O and Clock Planning - 2016.4 English - Introduces the I/O and clock resource planning features of the Vivado® Design Suite. Details creating and configuring I/O ports, grouping related ports into interfaces, and using automatic and interactive placement and design rule checks (DRC) to control port assignment onto FPGA package pins. - UG935

ug935-vivado-io-clock-planning-tutorial.pdf

Document ID
UG935
Release Date
2016-11-30
Version
2016.4 English