Vivado Design Suite Tutorial: Partial Reconfiguration - 2014.2 English - Demonstrates the creation of a Partial Reconfiguration (PR) design from HDL synthesis through BIT file generation using the Vivado® Design Suite. Partial Reconfiguration lets you reprogram and repurpose regions of an in-service Xilinx® FPGA with new functionality while the device continues to run. - UG947
ug947-vivado-partial-reconfiguration-tutorial.pdf
- Document ID
- UG947
- Release Date
- 2014-04-02
- Version
- 2014.2 English