Vivado Design Suite User Guide: Using Constraints - 2014.2 English - Describes using Xilinx® Design Constraints (XDC) in Vivado® tools. XDC combines industry-standard Synopsys Design Constraints (SDC) and Xilinx proprietary constraints. Details creating XDC to define clocks, I/O delays, and timing exceptions like false and multicycle paths, and min/max delays. - UG903

Document ID

UG903

Release Date

2014-05-13

Version

2014.2 English