Virtex-7 FPGA VC7203 Characterization Kit IBERT Getting Started Guide (Vivado Design Suite 2013.4) - 2013.4 English - This document provides a procedure for setting up the VC7203 Virtex-7 FPGA GTX Transceiver Characterization Board to run the Integrated Bit Error Ratio Test (IBERT) demonstration using the Vivado Design Suite. The demonstration shows the capabilities of the Virtex-7 XC7VX485T FPGA.