Virtex-7 FPGA VC7203 Characterization Kit IBERT Getting Started Guide (Vivado Design Suite 2013.2) - 2013.2 English - This document provides a procedure for setting up the VC7203 Virtex-7 FPGA GTX Transceiver Characterization Board to run the Integrated Bit Error Ratio Test (IBERT) demonstration using the Vivado Design Suite. The demonstration shows the capabilities of the Virtex-7 XC7V485T FPGA. - UG847

Document ID

UG847

Release Date

2013-07-09

Version

2013.2 English