LogiCORE IP ChipScope Pro IBERT for 7 Series GTH Transceivers - 2.00a English - The customizable LogiCORE IP ChipScope Pro Integrated Bit Error Ratio Test (IBERT) core for 7 series FPGA GTH transceivers is designed for evaluating and monitoring the GTH transceivers. This core includes pattern generators and checkers that are implemented in FPGA logic, and access to ports and the dynamic reconfiguration port attributes of the GTH transceivers. - DS873
ibert_7series_gth.pdf
- Document ID
- DS873
- Release Date
- 2012-04-24
- Version
- 2.00a English