LogiCORE IP JESD204 (v1.1) Data Sheet (AXI) - 1.1 English - The Xilinx LogiCORE IP JESD204 core implements a JESD204A or JESD204B interface supporting a line rate of up to 6.25 Gb/s on 1, 2 or 4 lanes using GTX transceivers in Virtex-6 and Kintex-7 FPGAs. The JESD204 core can be configured as Transmit or Receive. This document contains information about the AXI4 version of the core. - DS814

Document ID

DS814

Release Date

2011-10-19

Version

1.1 English