UltraScale Architecture FPGAs Memory IP v1.0 Product Guide - 1.0 English - Provides information about using, customizing, and simulating the DDR3 or DDR4 SDRAM, QDR II+ SRAM, or a RLDRAM 3 interface core. It also describes the core architecture and provides details on customizing and interfacing to the core. - PG150
pg150-ultrascale-memory-ip.pdf
- Document ID
- PG150
- Release Date
- 2015-11-05
- Version
- 1.0 English