Data Side OCM Bus v1.0 (v2.00a) Data Sheet - 1.0 English - The DSOCM Bus core is a data-side On-Chip Memory (OCM) bus interconnect core. The core connects the PowerPC 405 data-side OCM interface to OCM peripherals, such as the data-side OCM BRAM controller (DSBRAM_IF_CNTRL). - DS480
dsocm.pdf
- Document ID
- DS480
- Release Date
- 2007-01-22
- Version
- 1.0 English