Click the Address Editor window.
In the Address Editor, do the following:
a. Expand the microblaze_0 instance by clicking on the Expand All icon
in the toolbar to the top of the Address Editor window.b. Ensure the range of microblaze_riscv_0/mig_7_series_0/memmap IP in both the Data and the Instruction section are 512 MB, as shown in the following figure.
c. The top of the Address Editor window should show Assigned (11), indicating all 11 interfaces were assigned addresses. If Unassigned shows any interfaces unassigned, click on the Assign All arrow
.
You must also ensure that the memory in which you are going to run and store your software is within the cacheable address range. This occurs when you enable Instruction Cache and Data Cache, while running the Block Automation for the MicroBlaze V processor.
To use either Memory IP DDR or AXI block RAM, those IP must be in the cacheable area; otherwise, the MicroBlaze V processor cannot read from or write to them.
Validating the design will automatically re-configure the MicroBlaze V processor’s cacheable address range.