Step 1: Start the Vivado IDE and Create a Project - 2024.2 English

1. Start the Vivado IDE by clicking the Vivado desktop icon or by typing vivado at a command prompt.

2. From the Quick Start page, select Create Project.

3. In the New Project dialog box, use the following settings:

   a. In the Project Name dialog box, type the project name and location.

   b. Make sure that the Create project subdirectory check box is selected. Click Next.

   c. In the Project Type dialog box, select RTL project. Ensure that the Do not specify sources at this time check box is cleared. Click Next.

   d. In the Add Sources dialog box, set the Target language to either VHDL or Verilog. You can leave the Simulator language selection to Mixed.

   e. Click Next.

   f. In Add Constraints dialog box, click Next.

   g. In the Default Part dialog box, select Boards and choose Spartan-7 SP701 Evaluation Platform. Click Next.

   h. Review the project summary in the New Project Summary dialog box and click Finish to create the project.

Because you selected the SP701 board when you created the Vivado IDE project, you see the following message in the Tcl Console:

set_property board_part xilinx.com:sp701:part0:1.1 [current_project]

Although Tcl commands are available for many of the actions performed in the Vivado IDE, they are not explained in this tutorial. Instead, a Tcl script is provided that can be used to recreate this entire project. See the Tcl Console for more information. You can also refer to the Vivado Design Suite Tcl Command Reference Guide (UG835) for information about the write_bd_tcl commands.