•It is very important that the FPGA signal integrity of the JTAG TCK and FPGA CCLK signals are maintained. Avoid using lengthy connections where possible. Using long connections can result in unwanted noise or voltage waveform reflections that degrade the integrity of FPGA signals.
•Review the master SPI x4 schematic for the correct connectivity.
•Scope the CCLK, FCS_B, and D00_MOSI lines. After power-up or following a PROGRAM_B pulse, trigger on the falling edge of FCS_B and verify that the waveform matches the master SPI x1 or x4 read commands. Refer to the 7 Series FPGAs Configuration (UG470).
•For faster configuration and programming times, use the bitstream compression setting. For troubleshooting purposes, a simple bitstream can be used (that simply toggles a single LED or example) to get higher compression ratios and shorter programming times.
•Ensure the ConfigRate option does not exceed the maximum frequency supported by the target flash and FPGA. Refer to the FMCCKTOL timing parameter in the appropriate 7 Series device data sheet for the FPGA CCLK tolerance. For debugging, consider dropping the configuration rate lower than the maximum calculated frequency or even leaving it at the default. See SPI Flash Configuration Time for instructions on calculating the maximum configuration rate.
•Ensure the JTAG Integrity is good:
°Perform a basic FPGA IDCODE operation to verify the connections
°Program a simple bitstream into the FPGA
•Review the FPGA status register for additional insight. Figure 9. Shows the CONFIG STATUS register after a successful configuration.
|
X-Ref Target - Figure 20 |
