This section briefly overviews the various device configuration properties for 7 Series FPGA. Table: 7 Series Properties lists the necessary options to properly generate a configuration bitstream that is compatible with the SPI flash. If the option is unspecified, the default value is used.
|
Settings |
Default Value |
Possible Values |
Description |
|---|---|---|---|
|
BITSTREAM.CONFIG.EXTMASTERCCLK_EN |
Disable |
Disable, Div-1, Div-2, Div-4, Div-8 |
When set to disable, an internal oscillator is the source of the configuration clock (CCLK). When set to Div-1, Div-2, Div-4, or Div-8, the source of the CCLK is switched to the external clock source from the EMCCLK pin at the beginning of the configuration procedure. The CCLK frequency becomes the frequency of the EMCCLK source divided by the Div setting number. |
|
BITSTREAM.CONFIG.CONFIGRATE |
3 |
3, 6, 9, 12, 16, 22, 26, 33, 40, 50, 66 |
When the default internal oscillator is the source of the CCLK, this option sets the CCLK frequency. See the data sheet for the range of variation of the CCLK frequency when based on the internal oscillator. |
|
BITSTREAM.CONFIG.SPI_32BIT_ADDR |
No |
No, Yes |
Enables SPI 32-bit address style, which is required for SPI devices with storage of 256 Mb and larger |
|
BITSTREAM.CONFIG.SPI_BUSWIDTH |
None |
None, 1, 2, 4 |
Sets the SPI bus to Dual (x2) or Quad (x4) mode for Master SPI configuration from third party SPI flash devices. |
|
BITSTREAM.CONFIG.SPI_FALL_EDGE |
No |
No, Yes |
Sets the FPGA to use a falling edge clock for SPI data capture. This improves timing margins and may allow faster clock rates for configuration. |
|
CONFIG_VOLTAGE |
1.8 |
1.5, 1.8, 2.5, 3.3 |
Informs the tools of the voltage used for configuration. Set this to the voltage being used on the configuration banks. |
|
CFGBVS |
GND |
GND, VCCO |
Informs the tools of the voltage driving the CFGBVS pin. If the VCCO_0 supply for bank 0 is supplied with 2.5V or 3.3V, then the CFGBVS pin must be tied High (i.e. connected to VCCO_0) and CFGBVS property must be set to VCCO. If VCCO_0 is supplied with 1.5V or 1.8V, then the CFGBVS pin must be tied Low (i.e. connected to GND) and the CFGBVS property must be set to GND. |
|
BITSTREAM.GENERAL.COMPRESS |
False |
True, False |
Uses the multiple frame write feature in the bitstream to reduce the size of the bitstream, not just the Bitstream (.bit) file. Using compress does not guarantee that the size of the bitstream shrinks. |
These options are available through Device Properties in the Vivado Design Suite shown in the following figure.
|
X-Ref Target - Figure 7 
|
The Vivado IDE automatically sets the configuration properties in the design constraints (XDC) file, based on selections made in the Device Properties dialog, shown in This Figure. Alternatively, the following Tcl commands can be manually added to the XDC file:
set_property BITSTREAM.GENERAL.COMPRESS False [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR No [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
Note: The constraint example values above were used for the KC705 evaluation board.