This Equation should be used to determine the maximum frequency that the SPI flash can safely operate and still deliver the bitstream reliably. The SPI flash delivers data on the falling edge of the clock. The default for 7 series FPGAs is to capture data on the rising edge of the clock. For the equation below to be true, it is assumed that the SPI flash configuration option that enables the FPGA to capture data on the falling edge is enabled for Vivado Design Suite (set_property BITSTREAM.CONFIG.SPI_FALL_EDGE: YES) and for ISE Design Suite (bitgen -g spi_fall_edge: yes). This allows the full clock cycle to be utilized, therefore higher frequencies can be reached.
This Equation describes the SPI flash configuration frequency calculation.
In the 7 series FPGAs, the frequency tolerance of the internal oscillator (fMCCKTOL) is significant. If minimum configuration time is critical, it is recommended the designer use an external clock (EMCCLK).
After the optimum configuration rate is determined, the designer needs to divide the total bitstream size by the configuration rate to determine the total configuration time in x1 mode. If using x2 or x4 data widths, divide by the width.