Table: BitGen Configuration Options lists the BitGen options necessary to properly generate a configuration bitstream that is compatible with the SPI flash. These options are available through the Generate Programming File properties in the ISE tools shown in This Figure. If the option is unspecified, the default value listed first and displayed bold/ text is used.
|
BitGen Option |
Description |
|---|---|
|
-g spi_buswidth: 1|2|4 |
Selects the data width to be used when reading from the SPI flash. |
|
-g spi_32bit_addr: No|Yes |
Set to Yes when targeting a SPI flash 256 Mb or larger. This instructs the FPGA to transmit a larger address space required for larger flash devices. |
|
-g SPI_Fall_Edge: No|Yes |
Set to Yes when trying to achieve higher configuration speeds. Yes = capture data on the falling edge of the clock |
|
-g ConfigRate: 3|6|9|12|16| 22|26|33|40|50|66 |
Sets the approximate configuration clock frequency driven by the 7 series FPGAs to the SPI flash when using the internal oscillator (in MHz). The actual values for this option can be seen in UG628, Command Line Tools User Guide and might vary depending on the selected FPGA. |
|
-g ExtMasterCclk_en: Disable |div-8|div-4| div-2|div-1 |
Instructs the FPGA to use the clock signal on EMCCLK as the configuration clock instead of the internal oscillator. Select div-1 to use the clock on EMCCLK at the same frequency and the other div options to divide down the EMCCLK clock by the appropriate value prior to output on CCLK. |
To access these options from the ISE tools, right-click Generate Programming File then select Process Properties > Configuration Options. Alternatively, from the Process pull-down on the menu bar, select Process Properties, then select Configuration Options. From the Property display level pull-down at the bottom of the window, select Advanced to see all the options.
