SPI Flash Configuration Interface

This Figure shows the pins of the FPGA required for SPI flash configuration. Many of these pins are also required for other configuration methods and are not specific to SPI flash configuration.

Figure 3: 7-Series FPGA SPI Flash Configuration Interface Block Diagram
X-Ref Target - Figure 3

Table: SPI Flash Configuration Pins details the functions of the FPGA pins during SPI flash configuration. In addition to the pins mentioned in the SPI Flash Basics section, other configuration interface signals are shown which give status information and control of FPGA configuration.

Table 2: SPI Flash Configuration Pins
7-Series FPGA Pin Name	FPGA Direction	Dedicated or Dual Purpose	Description
M[2:0]	Input	Dedicated	Determines the FPGA configuration mode. M[2:0] = 001 for master SPI flash mode. Connect each mode pin either directly, or via a 1 kW (or stronger) resistor, to VCCO_0 or GND.
DIN/D[01]	Input	Dual-Purpose	Receives data from the SPI flash MISO pin. In x1 mode, this is the only data input pin to the FPGA.
D[00]	Input/Output	Dual-Purpose	At the start of FPGA configuration, this pin drives the SPI flash's MOSI pin and delivers a read instruction and the address. In x1 mode, this pin is output only. In x2 and x4 data width modes, this pin is bidirectional and receives data from the SPI flash.
D[02]	Input	Dual-Purpose	Receives data bit 2 from the SPI flash in x4 data width mode.
D[03]	Input	Dual-Purpose	Receives data bit 3 from the SPI flash in x4 data width mode.
INIT_B	Bidirectional, Input, Output, Open-drain	Dedicated	Driven Low during FPGA power-up, indicating the FPGA is performing self-initialization prior to initiating configuration. After self-initialization is complete, and before the mode pins are sampled, this pin can be externally driven Low to delay configuration. After mode pins are sampled, INIT_B becomes open drain. During configuration bitstream loading, this pin acts as an indicator for CRC error.
PROGRAM_B	Input	Dedicated	Active-Low asynchronous full-chip reset.
PUDC_B	Input	Dual-Purpose	Controls I/O (except bank 0 dedicated I/Os) pull-up resistors during configuration. This pin must be externally terminated. 0 = Pull-up resistors during configuration 1 = 3-state output during configuration
EMCCLK	Input	Dual-Purpose	An input for supplying an external configuration clock (optional). This clock is then internally routed to the CCLK FPGA pin.
CCLK	Input/Output	Dedicated	Initial configuration clock source for all configuration modes except JTAG. Drives the SCK pin of the SPI flash.
FCS_B	Output	Dual-Purpose	Drives the SPI flash SS/ pin Low during configuration to enable the SPI flash.
DOUT	Output	Dual-Purpose	Only used in x1 SPI flash configuration modes when daisy chaining multiple FPGAs. See UG470, 7 Series FPGAs Configuration User Guide for more information on daisy-chain configuration.
DONE	Output/ Open-Drain	Dedicated	Active-High signal indicating configuration is complete. 0 = FPGA not configured 1 = FPGA configured
CFGBVS	Input	Dedicated	For the Artix-7 and Kintex-7 families, this pin determines the voltage standard supported in the configuration I/O banks. For the Virtex-7 family, the only allowable configuration voltage is 1.8V or less. See the Configuration Bank Voltage Select section in UG470, 7 Series FPGAs Configuration User Guide for additional information. 1 = 2.5V or 3.3V 0 = 1.8V or less
TDI	Input	Dedicated	JTAG test data input port ⁽¹⁾
TMS	Input	Dedicated	JTAG test mode select input port ⁽¹⁾
TCK	Input	Dedicated	JTAG test clock input port ⁽¹⁾
TDO	Output/ open-drain	Dedicated	JTAG test data out port ⁽¹⁾
Notes: 1.JTAG pins are optional for the SPI flash configuration interface, but are required for indirect SPI flash programming.

This Figure and This Figure are nearly identical. This Figure illustrates the connections for a SPI flash configuration solution in x1 or x2 data width mode. This Figure illustrates the connections for a SPI flash configuration solution in x4 data width mode. The only difference between This Figure and This Figure is the handling of the HOLD and the W pins, which are terminated in x1 and x2 data width modes and are connected to the 7 series FPGAs in x4 data width mode.

Figure 4: SPI Flash x1/x2 Configuration Schematic
X-Ref Target - Figure 4

Notes relevant to This Figure, SPI flash x1/x2 configuration schematic:

1.DONE is by default an open-drain output. An external pull-up resistor is recommended.

2.INIT_B is a bidirectional open-drain pin. An external pull-up resistor is required.

3.CCLK signal integrity is critical.

4.Series resistors should be considered for the datapath from the SPI flash to the FPGA to minimize overshoot. The proper resistor value can be determined from simulation.

5.The VCCO supply of the 7 series FPGAs must be compatible with the VCC of the SPI flash. CFGBVS=GND when VCCO_0=1.8V or CFGBVS=VCCO_0 when VCCO_0=3.3V. (Flash [I/O] voltage, VCCO_0, VCCO_14, and CFGBVS must all be aligned hto support same voltage: 1.8V or 3.3V. 2.5V is also possible but not used since there is not any 2.5V SPI flash.

6.VCCBATT is the power source for the AES key stored in SRAM. For details about AES encryption, see UG470, 7 Series FPGAs Configuration User Guide.

Figure 5: 7 Series FPGA SPI Flash x4 Configuration Schematic
X-Ref Target - Figure 5

Notes relevant to This Figure SPI flash x4 configuration schematic:

1.DONE is by default an open-drain output. An external pull-up resistor is recommended.

2.INIT_B is a bidirectional open-drain pin. An external pull-up resistor is required.

3.CCLK signal integrity is critical.

4.Series resistors should be considered for the datapath from the SPI flash to the FPGA to minimize overshoot. The proper resistor value can be determined from simulation.

5.The VCCO supply of the 7 series FPGAs must be compatible with the VCC of the SPI flash. CFGBVS=GND when VCCO_0=1.8V or CFGBVS=VCCO_0 when VCCO_0=3.3V. (Flash [I/O] voltage, VCCO_0, VCCO_14, and CFGBVS must all be aligned to support same voltage: 1.8V or 3.3V. 2.5V is also possible but not used since there is not any 2.5V SPI flash.

6.VCCBATT is the power source for the AES key stored in SRAM. For details about AES encryption, see UG470, 7 Series FPGAs Configuration User Guide.