SPI Flash Basics

This section reviews the SPI flash pins and their connections to 7 series FPGAs. Details about the SPI flash configuration options, such as density selection, data width, and FPGA configuration time, are also included.

This Figure shows the basic connectivity between 7 series FPGAs and the SPI flash with a x1 data width. The read and address instructions are sent from the FPGA to the SPI flash via the master-out-slave-in (MOSI) pin. The data is returned from the SPI flash via the master-in-slave-out (MISO) pin. SCK is the clock pin and SS is the active-Low slave select pin. A x2 data width has the same connections, however the MOSI becomes bidirectional and is used as an additional data pin.

Figure 2: Basic SPI Flash to FPGA Connections—x1 Data Width
X-Ref Target - Figure 2

In addition to the pins described above, the SPI flash can have additional pins that can be used to control other special functions. These additional pins can vary with the SPI flash vendor, however two common special function pins are hold and write protect. Newer SPI flash devices enable these hold and write protect pins with a dual function of additional data output pins to increase the data bus up to 4 bits.

Table 1: SPI Flash Pin Names
Pin Names Used in This Document	Alternate Pin Names Used by Other Vendors	Pin Function
SCK	C, CLK	Clock for SPI flash instructions and data
MOSI	DQ0, DI, SI, IO0	Master out; slave in. Can be an additional data pin in x2 or x4 output modes
MISO	DQ1, IO1, SO, DO	Master in; slave out
SS	S/, CS/	Slave select
HOLD	DQ3, IO3	Hold or pause without deselecting the device. Can be an additional data pin in x4 output mode.
W	DQ2, WP/, IO2	Write protect portions of the SPI flash memory. Can be an additional data pin in x4 output mode.