The first step to programming the SPI flash in-system requires that the 7 series FPGAs is first loaded with an interface design that bridges the programming cable to the SPI flash. This step clears the contents of the FPGA. This SPI interface design leaves the unused FPGA pins floating. The user should be aware of this and ensure that this does not have any undesired effects on other devices attached to the FPGA. For example, certain I/O pins might need to remain Low or High during SPI flash programming. These pins would normally be pulled low or high by the final FPGA design. In these cases, the designer might need to add external pull-down or pull-up resistors on these pins to ensure correct behavior during SPI programming.
The following demonstration targets the Kintex-7 XC7K325T FPGA and the Micron MT25QL128 SPI flash present on the KC705 Kintex-7 FPGA evaluation board.
Ensure the board is powered and the USB cable is attached. In the case of the KC705 board, a standard USB-to-micro-USB cable is used instead of a platform cable USB II. In most cases, there is no specialized hardware on the board to handle the PC-to-JTAG interface so a Xilinx Platform Cable USB II or other supported cable is required.
1.Ensure the board is connected and a programming cable is connected. Turn on the power to the target board.
2.Open the Vivado tools Hardware Manager by selecting Open Hardware Manager under the Program and Debug flow as show in This Figure. Alternatively, select Flow > Open Hardware Manger.
3.Open and connect to the hardware target by clicking on the Open Target link in the Hardware Manager pane and then selecting Auto Connect as shown in This Figure.
Note: This step should automatically connect to the 7 series FPGA target if it is connected to the workstation that is running the Vivado Design Suite. Ensure the cable is properly connected and the board is powered on. It is also possible to connect remotely to another workstation that is running hw_server and is physically connected to the target board via a programming cable. See the Opening a New Hardware Target section in UG908, Vivado Design Suite User Guide: Programming and Debugging for a list of supported devices for more details if this flow is needed or auto connection fails.
4.Launch the Add Configuration Memory Device dialog by right clicking the target FPGA in the hardware manager as shown in This Figure.
5.In the Add Configuration Memory Device window, select the proper SPI flash from the list. The filter options and the search field can both be used to simplify the search and narrow down the options as shown in This Figure. Click OK.
Note: For SPI widths x1, x2, or x4, use SPI flash devices that end with "-x1_x2_x4" (or possibly "-x1" or "-x1_x2"), but not "-x1_x2_x4_x8". The latter is only for use with master SPI x8 configuration mode.
Note: Flash selection present on KC705 board is used.
6.Click OK in the Add Configuration Memory Device Completed dialog box that appears next to program the configuration memory devices at this time.
7.In the Program Configuration Memory Device dialog, click on the browse button to the right of the Configuration file field and select the .bin created previously. By default, the .bin file is located in the impl_1 project directory in the following subdirectory:
<Project_Dir>\<Project_Name>.runs\impl_1\
Note: The location of the Vivado tools project subdirectory is referred to as <Project_Dir> in this application note and the project name is referred to as <Project_Name>.
8.Set the Program Operations as needed for your design and click OK when finished (This Figure).
° Address Range: Specify to erase just enough sectors to cover the size of the programming file (Configuration File Only) or the entire SPI flash device (Entire Configuration Memory Device).
° Erase: Erase the sectors or the entire device as indicated by Address Range.
° Blank Check: Check that the sectors as indicated by Address Range are blank.
° Program: Program the SPI device with the Configuration file.
° Verify: Read back the programming contents and verify they match the Configuration file.
° SVF Options: An alternative way to program FPGAs and configuration memory devices is through the use of a serial vector format (SVF) file. The SVF file generated through Vivado® Design Suite and Vivado Lab Edition contains low level JTAG instructions and data required to program these devices. Refer to UG908, Vivado Design Suite User Guide: Programming and Debugging for more information.
Programming should begin as soon as OK is clicked. A Programming Configuration Memory Device window is loaded showing the progress of the various stages selected in the Program Operations dialog.