At power-on, a race condition exists between the FPGA and the SPI flash. After the FPGA completes a self-initialization, it transmits a read command to the SPI flash to retrieve the configuration data, at which time the SPI flash must be ready to respond to this command. Refer to the specifications in the SPI flash data sheets for the time required for the flash to complete its own self-initialization (see the References section for the list of SPI flash data sheets). In general the self-initialization time (also called power-on reset) of the 7 series FPGAs is an order of magnitude (milliseconds) more than the SPI flash (hundreds of microseconds), however the designer should evaluate the time. This is certainly more important if the SPI flash and the FPGA are on different supply rails.