This application note addresses the two flows shown in This Figure:
•Indirect SPI flash programming using the Vivado Design Suite and ISE Design Suite iMPACT tools.
•SPI flash configuration that delivers the FPGA configuration bitstream stored in a SPI flash memory to the 7 series FPGAs.
Xilinx FPGAs require that a configuration bitstream is delivered at power-up. The SPI flash memories use a 4-wire synchronous serial data bus. The SPI flash configuration requires only four pins, which allows 1- or 2-bit data width for delivery of the configuration bitstream. Newer SPI flash devices offer the option to use six pins to enable 4-bit data width, thereby decreasing configuration time appropriately. FPGA configuration via the SPI interface is a very low pin count configuration solution and many vendors have devices in a large range of density options.
Other options for FPGA configuration, such as a byte peripheral interface (BPI) parallel NOR flash, supports a wider configuration data bus that allows for faster configuration at power-up, however this mode requires a minimum of 25 pins.
Because parallel NOR flash devices have higher density options than SPI flash, BPI flash should be considered if the application requires large amounts of nonvolatile data storage or if several FPGA bitstreams need to be stored.
Xilinx also provides the ability to program the SPI flash in-system using the existing configuration connections between the SPI flash and the FPGA. The Xilinx programming tool uses JTAG to configure the FPGA to enable a path between the configuration cable and the SPI flash. This allows design flexibility in a lab environment to easily program new configuration bitstreams into the SPI flash without removing the flash from the board and using an external desktop programmer.
The sections in this document are:
•SPI Flash Basics: Review of the SPI flash pin functions and device features.
•SPI Flash Configuration Interface: Details on the FPGA configuration interface with the SPI flash.
•SPI Flash Configuration Time: Details the steps for determining the maximum clock frequency.
•SPI Flash Using Xilinx Vivado Design Suite
°SPI Flash Using ISE Design Suite: Describes the option for generating the bitstream.
°Preparing the SPI Flash Programming File: Vivado Design Suite IDE Example: Provides the instructions to generate a SPI flash data file.
°Programming the SPI Flash In-System: Vivado Design Suite IDE Example: Provides instructions to program the SPI Flash.
•SPI Flash Using ISE Design Suite
°SPI Flash Configuration Options: Describes the options for generating the bitstream.
°Preparing the SPI Flash Programming File: Provides instructions to generate a SPI flash data file.
°Programming the SPI Flash In-System: Provides instructions to program the SPI flash.