Generating Bitstream: Vivado Tools TCL Batch FILE Example

Using SPI Flash with 7 Series FPGAs (XAPP586)

Document ID
XAPP586
Release Date
2022-12-09
Revision
1.5 English

As an alternative to the IDE flow presented in the previous section, a TCL batch file is presented here that can be used with a non-project Vivado tools flow. There must have been a checkpoint created previously for this flow to succeed. This script assumes the checkpoint is saved in a subdirectory of the current directory from where the script is run:

## Non-project TCL flow to generate a BIN file used for SPI Flash programming

# Note: write_checkpoint must have been run prior to running this script open_checkpoint (post_route.dcp)

set_property BITSTREAM.GENERAL.COMPRESS FALSE [current_design]

set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design]

set_property CONFIG_VOLTAGE 3.3 [current_design]

set_property CFGBVS VCCO [current_design]

set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR hNo [current_design]

set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]

set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]

write_bitstream -verbose -force -bin_file spi_programming.bit

Note:   The example above are constraints used on KC705 evaluation board.