After the FPGA finishes self-initialization, INIT is released and the FPGA samples the mode pins (M[2:0]) to determine which configuration mode to use. With the mode pins M[2:0] = 001, the FPGA then begins to output clocks on CCLK at a frequency of approximately 3 MHz. Shortly afterwards, FCS_B drives Low, followed by the OPCODE for a x1 fast-read instruction and address on the D[00] pin as shown in This Figure.
Data is initially transmitted from the SPI flash to the FPGA in x1 mode. The commands to switch to an external clock, x2 or x4 bus width, or other options are all contained within the early portion of the bitstream. After reading these options, the FPGA makes mid-configuration adjustments.
The default behavior is for data to be output from the SPI flash on the falling edge of CCLK and captured by the FPGA on the rising edge of CCLK. The default behavior can be changed to capture on the falling edge by enabling the option set_property BITSTREAM.CONFIG.SPI_FALL_EDGE: YES” (Vivado Design Suite) and bitgen -g SPI_FALL_EDGE:yes (ISE Design Suite).