This section demonstrates the steps to determine the maximum operating configuration frequency for the SPI flash solution.
The SPI flash selected is N25Q128A13 and the target is a Kintex-7 XC7K325T FPGA.
The SPI flash clock to out, per the SPI flash data sheet, has multiple values depending on VCC and the capacitance on the output pin.
These values are as fast as 5 ns and as slow as 7 ns according to the N25Q128A13 data sheet. In this example, the value of 7 ns represents the SPI flash operating with a load of 30 pF or less.
The FPGA setup time for a Kintex-7 XC7K325T FPGA is 3.0 ns (for the current value, refer to DS182, Kintex-7 FPGAs Data Sheet).
The trace propagation delays from the CCLK to C pin and the longest propagation delay of any of the data pins provide TTPD. For this example, a rule of thumb of 165 ps per inch and a trace length of 6 inches from the FPGA to the SPI flash are used. (For more accurate results, other techniques such as IBIS simulation are recommended.) A trace value of 12 inches at 165 ps/inch gives 2.0 ns.
1 / (7 ns + 3.0 ns + 2.0 ns) yields a clock frequency of 83.3 MHz.
The designer should consider using the FPGA's internal oscillator and the closest value to 83.3 MHz is 66 MHz. However, the frequency tolerance (fMCCKTOL) for the XC7K325T is ±50% (for the current value, refer to DS182, Kintex-7 FPGAs Data Sheet) so this clock frequency could potentially be (66 MHz x 1.5) = 99 MHz, which would be too fast for the calculated maximum.
The next fastest configuration rate is 50 MHz, which has a maximum frequency of (50 MHz x 1.5) = 75 MHz. This rate is well below the calculated maximum and nominally operates at 50 MHz, which is well below the desired 83.3 MHz.
The bitstream of a Kintex-7 XC7K325T FPGA is 91,548,896 bits.
91,548,896 / 50,000,000 = 1.83 seconds to configure XC7K325T in x1 data width @ 50 MHz
Assume that an 80 MHz oscillator was already on the board for another application or device, and so can serve a dual purpose as the clock for the FPGA configuration.
91,548,896 / 80,000,000 = 1.144 seconds to configure XC7K325T x1 data width @ 80 MHz
1.144 / 4 = 286 ms to configure the XC7K325T FPGA in SPI flash x4 data width