Download the reference design files for this application note from the Xilinx website. The following checklist summarizes the hardware and software changes required to support DVS.
| Parameter | Description |
|---|---|
| General | |
| Is DVS required? | DVS is required for AMD Versal™ -2LI devices. |
| Is the recommended PLM/AMD drivers solution used? | The AMD verified solution contained within the PLM should be used. |
| Is the recommended -2LI rail consolidation used? | This rail consolidation breaks out the VCCINT rail because its voltage is unique to that rail and cannot be consolidated with any other voltages. |
| Hardware | |
| I2C/PMBus compatible voltage regulator used? | I2C/PMBus is required to change the voltage on VCCINT. |
| Are there other primary I2C/PMBus devices on the same bus? | The DVS drivers require primary capabilities to drive the clocks on the bus and signal when the voltage change is required. |
| Default/start-up voltage set to 0.725V? | This must be the default voltage on power-up. |
| Software | |
| Synthesis software tools/versions used | AMD Vivado™ Design Suite 2022.2 |
| Is the software driver implemented? | Functionality tested using baremetal driver |
| Any platform software changes needed? | CDO regulator changes are required before generating the PDI. |