Via Impedance Optimization - Via Impedance Optimization - XAPP1392

PCB Channel Design Guidelines for 112 Gbps GTM Transceivers (XAPP1392)
Document ID
XAPP1392
Release Date
2023-05-23
Revision
1.0 English
  • PCB vias are a source of impedance discontinuities if not properly designed. The via stub, antipad size, drill hole size, and differential via pitch are important features for via impedance control.
  • Minimizing via stub is crucial for securing 112 Gbps channel designs. A via stub can cause a ¼ wave resonance. At the resonance frequency, a deep notch appears on the insertion loss due to the cancellation between the 180-degree out-of-phased reflected signal from the stub and the transmitting signal. The resonance frequency can be estimated as follows.
    Figure 1. ¼ Wave Resonance Frequency
    Where fres is the ¼ wave resonance frequency, c is the speed of light in vacuum, l is the stub length, and Dkeff is the effective dielectric constant the via sees. Dkeff is normally higher than the PCB dielectric material’s dielectric constant because of the coupling between via barrel/pads and the reference planes surrounding the via. To minimize the impact of the ¼ wave resonance on the signal, it is recommended to push the resonance frequency well above the signal bandwidth, for example, > 2 × signal bandwidth.
  • The most common way to match via impedance with channel nominal impedance is tuning the via antipad size to adjust the capacitance and inductance ratio. However, a small via antipad is preferred in the ball grid array (BGA) pin field to reduce the trace-via crosstalk. For the BGA via impedance optimization, return loss and crosstalk should be evaluated simultaneously to determine the optimal point for maximal system margin.
  • For the blind via, extending the antipad void to the layers beneath the via mitigates the excess capacitance from the coupling between the via pad and the planes. For a blind via with a lead-out trace not routed on the bottom layer of the via, for example a blind via in sequential lamination, removing the via bottom layer pad like a landless via helps with minimizing the capacitance as well, as shown in the following figure.
    Figure 2. Landless Blind Via
  • Unlike the 25 Gbps NRZ / 56 Gbps PAM4 channel where an identical antipad on all the layers is sufficient for optimal via impedances in the frequency band of interest, tuning the antipad size/shape per layer is necessary to keep a low return loss for the wider frequency band in 112 Gbps designs.
    • The antipad voids on the stripline reference plane layers have a significant impact because of the excess inductance from the lead-in/out trace losing its reference in the void range.
    • The antipad void on layer 2 has a significant impact because of capacitive coupling to the top layer pad.
  • Spacing of the signal and GND vias has a significant impact. Outside the BGA pin field, the GND vias should be placed as close to the signal via as possible, but not encroach into the signal via antipad void range. In the BGA pin field, the placement of GND vias should follow the pattern of GND balls.