High-speed data rate transmissions suffer from distortions to the signal imposed by channel response. 112 Gbps continues to push channel design considerations, both at the board level and in the transceiver. The small unit interval of the symbol combined with the reduced eye amplitude of the 4-level pulse amplitude modulation (PAM4) scheme results in less available budget for impairments, such as crosstalk and jitter. This application note details printed circuit board (PCB) channel design requirements for high-speed serial data transmission, including rates of 56 Gbps and 112 Gbps. Good practices for minimizing and mitigating the various impairments on the PCB are also presented.
Download the reference design files for this application note from the Versal ACAP Transceiver IBIS-AMI Model Secure website. For detailed information about the design files, see Reference Design.