Optimal Channel Nominal Impedance - Optimal Channel Nominal Impedance - XAPP1392

PCB Channel Design Guidelines for 112 Gbps GTM Transceivers (XAPP1392)

Document ID
XAPP1392
Release Date
2023-05-23
Revision
1.0 English
  • When there are large discontinuities that cannot be eliminated, the optimal trace impedance should be determined in a way that minimizes the multiple reflections from the discontinuities. It is not necessary to adhere to 100Ω or 85Ω.
  • The nominal trace impedance of the Versal device GTM transceiver channel package is 92 ~ 93Ω ± 10%.
  • The channel nominal impedance should be selected per system-level SI analysis with all discontinuities included.
Figure 1. Discontinuity Examples

As illustrated in the previous figure, discontinuities usually occur at vertical transition regions, like package-to-PCB interfaces and PCB-to-connector interfaces. Attention to detail at every signal transition region is critical to achieve a successful 112G channel design.

Important: The recommended channel return loss requirement is as follows:
  • PCB differential return loss (@ ≤ Nyquist): ≤ –12 dB [at the solder ball]
  • PCB common-mode return loss (@ ≤ Nyquist): ≤ –15 dB
  • PCB differential-to-common mode return loss (@ all frequencies): ≤ –15 dB
  • PCB common-to-differential mode return loss (@ all frequencies): ≤ –15 dB