When data rates approach 56 Gbps per lane, a more bandwidth-efficient modulation scheme (PAM4) is deployed. However, PAM4 signaling is susceptible to noise, including intersymbol interference (ISI) and crosstalk, because the eye height is reduced while still generating full amplitude signal swings. The result is the potential worst-case condition of the signal aggressor having a full height voltage transition, while the victim simultaneously has a swing of 1/3 the full height.
As shown in the following figure, taken from Overview of ADC-based Wireline Transceiver [1], suppose the designed channel has 10% reflection at the fifth cursor h5, the amplitude of Bit 5 (green waveform) is h (minor transition from 1/3 to –1/3). For a major transition Bit 0 (from –1 to 1) with amplitude of 3 × h occurs at cursor h0 (red waveform), the amplitude of the reflected signal at the fifth cursor h5 is 0.3 × h (10% × 3 × h), which is 30% of Bit 5’s amplitude h. The impact of the residual ISI on PAM4 is three times its non-return-to-zero (NRZ) counterpart.
As data rates increase further to 112 Gbps, the unit interval is less than 20 picoseconds. Large numbers of DFE or FFE taps at the RX side are required to manage the multiple reflections from discontinuities that show up far away from the main cursor. A Tutorial on PAM4 Signaling for 56G Serial Link Applications [2] provides a thorough review of PAM4 signaling.
The small unit interval combined with PAM4 modulation reduces channel design budget to the point where each element in the channel matters. Besides meeting the channel insertion loss budget, dedicated design efforts should be taken to minimize impedance discontinuity, crosstalk, and skew on the channel.
High-speed data rate transmissions suffer from distortions to the signal imposed by channel response. The most significant impairments from the passive channel include:
- Frequency-dependent attenuation and dispersion from conductor loss and dielectric loss lead to insertion loss (IL).
- Reflections/multiple reflections from discontinuities and impedance mismatch lead to return loss/effective return loss (RL/ERL).
- Crosstalk due to unwanted horizontal coupling and vertical coupling lead to power sum crosstalk (PSXT), insertion loss to crosstalk ratios (ICR), and integrated crosstalk noise (ICN).
- Intra-pair skews originating from asymmetry structure, glass weave, and trace length mismatch lead to mode conversion (SDC/SCD).
The GTM transceiver in the AMD Versal™ adaptive SoC is a dual-mode, multi-protocol transceiver supporting multiple electrical standards, including OIF CEI-56G-VSR/MR/LR [3], and IEEE 802.3bs/cd/ck [4]. It addresses both in-box and out-of-box interconnects, from short reach to long reach (LR) chip-to-chip interfaces within the PCB and across the PCB through board-to-board connecters or direct attached cables (DAC), optical interfaces through pluggable optical modules, or the emerging technology of on-board optics/near-package optics [5].
This application note details the requirements and good practices for minimizing and mitigating various impairments and achieving successful 112 Gbps high-speed serial link designs. These requirements are provided with the channel requirements of any supported protocol. Supported protocols are listed in the datasheets for the Versal devices with GTM transceivers.