As mentioned in the Crosstalk section, a BGA pin field is a high crosstalk region due to via-via and trace-via coupling from the limited routing space. This section details important design considerations for the VP1802 C4072 package PCB breakout. These considerations should be carefully studied when using full Versal device GTM transceiver Quads for 56 Gbps LR-LR and VSR-LR reach applications. When using half of the channels in each of the Versal device GTM transceiver Quads, 112 G LR-LR operation is achievable by following the same design considerations. For designs that exceed these guidelines, consider using the A5601 package instead which supports 56 Gbps full-density Versal device GTM transceiver Quad implementation from VSR to LR reaches. See Versal Adaptive SoC Packaging and Pinouts Architecture Manual (AM013) for the design considerations regarding the A5601 package.