C4072 Package PCB Breakout Design Guidance - C4072 Package PCB Breakout Design Guidance - XAPP1392

PCB Channel Design Guidelines for 112 Gbps GTM Transceivers (XAPP1392)

Document ID
XAPP1392
Release Date
2023-05-23
Revision
1.0 English

The recommendations for the C4072 package PCB breakout are summarized as follows.

  • TX-to-RX isolation must be carefully considered, especially for LR applications
  • RX-to-RX isolation for large IL variations must be carefully considered
  • Route TX on lower layers rather than RX to avoid trace-to-via coupling
  • Provide ~18 mil separation between RX and TX routing layers
  • Place GND vias outside BGA pins to improve RX-to-RX isolation

For a 56 Gbps full-density Quad usage, recommendations are as follows:

  • TX-to-TX crosstalk
    • Worst-case TX victim: Four diagonal aggressors (plus two non-diagonal aggressors separated by a pair of GND balls)
    • Middle column of TX pins routed with via length less than 45 mil
    • Victims with fewer aggressors can have longer vias
  • RX-to-RX crosstalk
    • Worst-case RX victim: Four diagonal aggressors (plus two non-diagonal aggressors separated by a pair of GND balls)
    • Projected power sum crosstalk at < 14 GHz = –44 dB
    • Recommended restriction: Insertion loss delta between RX channels: < 14 dB
  • TX-to-RX crosstalk
    • For LR RX with 35 dB insertion loss, requirement is 65 dB isolation
    • TX routing layer must be at least 18 mil below lowest RX routing layer