C4072 BGA Pin Pattern Examples - C4072 BGA Pin Pattern Examples - XAPP1392

PCB Channel Design Guidelines for 112 Gbps GTM Transceivers (XAPP1392)

Document ID
XAPP1392
Release Date
2023-05-23
Revision
1.0 English

The BGA pin pattern examples for 56 Gbps full-density Quad usage are illustrated in the following figure. As shown in the figure, the RX pairs are located along the periphery of the BGA. TX pairs are located at the interior with one column of GND balls for TX-to-RX isolation. The worst-case victim RX/TX pair is surrounded by four diagonal aggressors plus two non-diagonal aggressors separated by a pair of GND balls. In addition to the RX-to-RX/TX-to-TX crosstalk, the trace-via coupling due to the TX pair lead-out traces routed near the RX pair via barrels can jeopardize the TX-to-RX isolation.

Figure 1. BGA Pin Pattern Examples – 56 Gbps Quad

GTM transceivers can operate at data rates up to 112 Gbps by using two out of the four transceivers in each Quad. As illustrated in the following figure, by choosing one of (Lane0 or Lane1) and one of (Lane2 or Lane3) in a Quad, both TX-to-TX and RX-to-RX crosstalk are limited to one diagonal aggressor. Therefore, the minimum isolation targets are easier to achieve without strict layout guidelines.

Figure 2. BGA Pin Pattern Examples – 112 Gbps Dual

The crosstalk components depicted in Figure 2 are listed below and illustrated in the following figure.

TX-to-TX coupling
Dominated by via-via coupling and occurs at BGA pin
RX-to-RX coupling
Dominated by via-via coupling and occurs at BGA pin
TX-to-RX coupling
Dominated by trace-via coupling and occurs at RX BGA pin
Figure 3. Crosstalk Components in BGA Pin Field