Monophase DPD on AI Engine

Automatic Digital Pre-distortion Design Generation for AI Engine (XAPP1391)

Document ID
Release Date
1.0 English

For AI Engine running at 1 GHz, monophase DPD supports up to 983.04 MSPS sample rate. Every AI Engine can process up to 16 LUTs, and the example shown in the following figure can have up to 64 LUTs. The computation results of one AI Engine are in 48-bit I and 48-bit Q format transferred to the next AI Engine via the cascading bus until the end of the chain where the final accumulation result is shifted, rounded, and saturated to 16-bit I and 16-bit Q format. The input data and the magnitude are broadcasted to all AI Engines but might be consumed at different times depending on the delays of the LUTs. DMA FIFOs are inserted in the data buses to absorb the differences in delays and avoid deadlocks. The magnitude values are used to address the data memory. Because AI Engine can perform two memory loads of 256 bits in one clock cycle, two double memory banks are allocated for up to (256 × 2/32 = 16) LUTs per AI Engine.

Figure 1. Monophase DPD Implementation on AI Engine

A single AI Engine can compute the following mathematical equation at 983.04 MSPS throughput at 1 GHz clock.

Figure 2. GMP Terms Mapped to One AI Engine

The LUT configuration is determined by the parameters {d, m, v, r, h0, h1, h2, h3}. Without loss of generality, h0 is always selected to be 0 and the set of parameters {d, m, v, r, h1, h2, h3} are visualized in the following figure.

  • 16 LUTs must consist of four identical parallelograms which are shown in different colors in the figure.
  • The leftmost LUT has a sample delay d, and that of the upper left LUTs of the other three parallelograms are d + h1, d + h2, and d + h3, respectively.
  • The top LUT has a magnitude timing offset m, and that of the upper left LUTs of the other three parallelograms are m + 1, m + 2, and m + 3, respectively.
  • The lower LUTs of each parallelogram have an extra magnitude delay of v.
  • The LUTs on the right-hand side have an extra magnitude delay of s and sample delay of r.

The above parameters determine the LUT configuration without ambiguity. Moreover, these parameters must satisfy the following requirements for a successful mapping to AI Engine:

  • s = 0 or 1
  • v ≤ 6
  • Define H’= {0, 1 – h1, 2 – h2, 3 – h3}. max(H’) – min(H’) + r ≤ 5
Figure 3. Diagram of Parameters for a Single AI Engine LUT Configuration

It has been checked that a total of 2400 legitimate LUT configurations can be described by the parameters {d, m, v, r, h1, h2, h3} and mapped to one AI Engine. As an example, the following lines describe a LUT configuration shown in the following figure, where LUTs in each color are mapped to the same AI Engine.

Figure 4. Example of Parameters for LUT Configuration