Obtaining Thermal and Power Targets to Use with Thermal Simulation - XAPP1377

Prior to running a thermal sim, the power dissipation and temperature targets for the device need to be understood. As for thermal targets, it is best to first understand the minimum and maximum device operating temperatures for the device. This can be obtained from the appropriate AMD product selection guide or data sheet. In general, most devices fall into one of four classifications.

For devices offering excursion temperature operation, the junction temperature might be able to operate at higher temperatures for short periods of time. To use this thermally beneficial feature, a mission profile needs to be generated and evaluated for the design. For more information on generating a mission profile and using an excursion temperature, refer to Extending the Thermal Solution by Utilizing Excursion Temperatures (WP517).

For devices using HBM memories, the additional step of setting temperature goals for HBM operation must also be taken. The maximum operating temperature for HBM memories is 95°C for constant operation. For the AMD Virtex™ UltraScale+™ and AMD Versal™ devices with –2 LE speed grade, excursion temperature operation can be up to 105°C for a limited time. Higher operating temperatures can impact refresh rates that affect the operational bandwidth, so that should be taken into consideration when setting HBM memory target temperatures.

Determining the target temperature for simulation depends on design goals. Often the target is set to the maximum operating temperature of the device or the calculated excursion temperature if allowed by the device and design. However, sometimes a lower target temperature is desired. For instance, if minimum operating power is desired, further reduction of the junction temperature results in less power dissipation in the devices. Another example is in the case of a handheld unit. Sometimes lower operating temperatures are necessary so as to not burn the user or keep battery or other component temperatures within reasonable limits. In any case, one of the first steps prior to thermal simulation is determining the appropriate junction temperature target for the application.

AMD FPGAs and adaptive SoCs do not have a total design power (TDP) specification due to their adaptability and the fact that customers use them for a variety of applications across many industries. As a result, AMD offers a selection of tools. The Xilinx Power Estimator (XPE) is available for early estimation of older device series. The Power Design Manager (PDM) is available for newer series from 16 nm onwards, such as AMD UltraScale+™ and the AMD Versal™ family. Some device series are supported by both estimation tools, and the recommendation is for new designs to start with PDM. The following table shows the available power estimation tools for the AMD FPGAs and adaptive SoCs.

For Kria SOM users, the PDM tool is used to determine power dissipation and apply predicted power to the SOM thermal model. After the tool is properly filled out, you can find the power to be applied to the simulation in the total on-chip power section of the tool. The tools can be obtained from the Power page of the AMD website.

For accurate power estimation, the static component should be estimated based on thermal simulation results. This can be done in the Summary > Enviornment section. It is done in one of the following two ways:

• Force the junction temperature to the simulation result. While this estimates static power at a fixed junction temperature, it does not adjust junction temperature based on increases or decreases in the dynamic power.
• Apply the maximum ambient temperature Ta and the effective Theta Ja from thermal simulation to XPE or PDM. This allows the estimator to adjust the junction temperature based on the estimated dynamic power and the effectiveness of the thermal solution.

For devices using HBM memories, the HBM target temperature and power summaries can be found in the following summary table on the Summary page. Two power entries should to be provided to the simulation model: one for the FPGA and one for the HBM stacks. Both can be obtained from the summary table in PDM or XPE. Even for devices that contain multiple die or HBM stacks, only a single power value for each should be provided to the model comprising the total power of all die or stacks.