The unique power architecture of Versal and AMD Zynq™ UltraScale+™ devices allows for power sequencing of other power domains and power savings by employing power management using the processing system (PS). The PS low power domain (LPD) can implement power sequencing for other power domains within Versal or Zynq UltraScale+ devices such as the full power domains (FPD), programmable logic, system, or AI Engines without impacting LPD or PMC functions. The LPD real-time processor allows for bare-metal programs that employ power sequencing for these other power domains. This domain remains powered when powering up/down of other domains dynamically as the need arises. Power sequencing or power management is capable through I/Os, PMBus, or I2C using the built-in controllers. See Controlling the Versal Power Domain Using GPIO in Versal Adaptive SoC System Software Developers Guide (UG1304) for more information.
Figure 1. Using MIOs to Sequence by Power Domain
