Versal Adaptive SoC Test Bench

Two hardware test benches are delivered with this application note. The first is for the GTY transceiver and runs on the VPK190 evaluation board. The second is for the GTM transceiver and runs on the VPK120 evaluation board. Both test benches can be implemented to show the NIDRU data recovery capability with both synchronous and asynchronous inputs.

To compile the test benches, source the nidru_design_versal.tcl script from the Vivado Design Suite. The test bench architecture is shown in the following figure.

Figure 1. TB_HW_DRU Test Bench Architecture

The test bench includes:

A 25G receiver, based on the NIDRU, operating on a 156.25 MHz reference clock.
The TX channel transmits data synchronized with REFCLK 200 MHz. The channels are connected via a SFP cable so that the receiver receives data at a frequency not synchronized to its own reference clock.

The two reference clocks are generated on board by using the system controller. The reference clock frequencies are configured through the ethernet interface by using the Board Evaluation and Management (BEAM) Tool.
TX side
A PRBS generator continuously sending a PRBS 7 or PRBS 31 pattern. Each of the two PRBS generators can be forced to generate an error using the Vivado Logic Analyzer to show error detection on the corresponding PRBS checker.
RX side
A PRBS checker continuously checking the incoming PRBS 7 or PRBS 31 pattern. The ERR output indicates detection of at least one error from the last ERR_RST. ERR is connected to the virtual input/output (VIO) and checked in real time. An error counter is also provided.

The specific PRBS pattern used in this application note for both the generator and the checker is based on the polynomial x31+x28+ 1 for PRBS 31, x7+x6+ 1 for PRBS 7 and can be changed to any other industry standard PRBS type.

Each PRBS checker works on the data delivered by the barrel shifter, which is instantiated right after each NIDRU block. The following figure reports the detailed description of all signals of the test bench that are controlled by the Vivado Logic Analyzer. The pin names are consistent across the VHDL code, the logic analyzer project, and this application note.

Figure 2. Vivado Logic Analyzer Controlling the Demonstration Test Bench

The transmitter can be set to generate a PRBS pattern, as described previously. When the application works properly, all LEDs are green. In case of an error in the datapath, the corresponding LED (highlighted with dashes in the previous figure) for the chk_okko_gt0 signals is red. The example design needs two asynchronous and independent clocks. For the receiver, the frequency is 156.25 MHz. The clock for the transmitter can be a different frequency accordingly to the selected data rate.

Both VCK190 and VPK120 boards provide the required clocks through the system controller. In the example design supplied with this application note, the system controller can be programmed by the BEAM tool and using the ethernet interface. The information to program the reference clock for the VCK190 board can be found at BEAM Tool for VCK190 Evaluation Kit.

The following figure shows the settings for generating the correct frequency of 156.25 MHz.

Figure 3. Receiver Clock Setup for the VCK190 Board

The following table shows the data rate and the frequency value to be set in the BEAM tool.

Table 1. Data Rate and TX Frequency Setup for the VCK190 Board
	CONFIG 0	CONFIG 1	CONFIG 2	CONFIG 3	CONFIG 4	CONFIG 5	CONFIG 6
Rate (Gb/s)	1.25	2	2.5	3	3.5	4	8
TX ref clock (MHz)	200	200	200	150	175	200	200

The following figure shows the settings for generating the correct frequency for the transmitter.

Figure 4. Transmitter Clock Setup for the VCK190 Board

The information for the VPK120 board can be found at BEAM Tool for VPK120 Evaluation Kit. The following figure shows the settings for generating the correct frequency for the receiver at 156.25 MHz and transmitter at 200 MHz.

Figure 5. Clock Setup for the VPK120 Board

The following table shows the data rate and the frequency value to be set in the BEAM tool.

Table 2. Data Rate and TX Frequency Setup for the VPK120 Board
	CONFIG 0	CONFIG 1	CONFIG 2	CONFIG 3	CONFIG 4
Rate (Gb/s)	1.25	2.5	3	3.5	7.5
TX ref clock (MHz)	200	200	200	200	200

The following figure shows the correct clock configuration after setting the frequency for the transmitter and receiver.

Figure 6. Transmitter and Receiver Clock Configuration for the VPK120 Board

To test the eye scan feature, configure the ILA Capture Mode Settings and Trigger Mode Settings as shown in the following figure.

Figure 7. Vivado Logic Analyzer ILA Settings

The trigger is done on the rising edge of the signal EN_ERR_COUNT_0 asserting the signal START_EYESCAN available in the VIO window.

The following figures show a hardware eye scan with PH_NUM = 1 and PH_NUM = 2, respectively.

Figure 8. Eye Scan with PH_NUM=1 (this is a Hardware Measurement)

Figure 9. Eye Scan with PH_NUM=2 (this is a Hardware Measurement)

Versal Adaptive SoC Test Bench - XAPP1362

Non-Integer Data Recovery Unit (XAPP1362)