The IMR register is shown in the following table. For each violation
interrupt mask bit:
- 0: enabled.
- 1: masked (disabled). If the ISR bit = 1 (asserted interrupt) and the IMR bit = 0 (not masked), then the IRQ to the interrupt controller is asserted.
Software checks the ISR to determine the cause of the interrupt. Read only.
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:4 | ro | 0x0 | Reserved |
| SecurityVIO | 3 | ro | 0x1 | Security violation by AXI master |
| WrPermVIO | 2 | ro | 0x1 | Write Permission violation by AXI Master |
| RdPermVIO | 1 | ro | 0x1 | Read Permission violation by AXI Master |
| Reserved | 0 | ro | 0x0 | Reserved |