TMR MicroBlaze CPU - TMR MicroBlaze CPU - XAPP1336

Isolation Design Example for the Zynq UltraScale+ MPSoC (XAPP1336)

Document_ID
XAPP1336
Release_Date
2023-10-20
Revision
2.1 English
  1. Create a Hierarchy temporarily for microblaze_0 and microblaze_0_local_memory. Select both the IPs, right-click, and then click on Create Hierarchy. Refer to the following figure.
  2. Name the cell as MB_SYSTEM, select Move 2 selected blocks to new hierarchy, and then click OK. Refer to the following figure.
  3. Add TMR Manager IP under MB_SYSTEM by expanding the MB_SYSTEM. Then right-click in the MB_SYSTEM box and click ADD IP. Refer to the following figure.
  4. Click Run Block Automation, keeping the default selected values for tmr_manager, and click OK on the Run Block Automation window.
  5. Ungroup the MB_SYSTEM hierarchy. Select MB_SYSTEM hierarchy and right-click. Then click Ungroup Hierarchy.
  6. Right-click on an empty space in the canvas and select Regenerate Layout. When you are finished, the IPI canvas looks like the following figure.