This lab application note describes the creation and implementation of a single-chip general purpose two-channel compute system using the Low Power Domain as one channel and a triple modular redundant MicroBlaze™ processor in the programmable logic (PL) as another channel and both being interconnected by a Mailbox, which is also implemented in the PL.
Complete step-by-step instructions are given for the entire process, explaining the use of the Isolation Design Flow (IDF). This document explains how to implement isolated functions in a single AMD Zynq™ UltraScale+™ device for the example solution.
With this application note, designers can develop a fail-safe single chip solution using the AMD IDF that meets fail-safe and physical security requirements for an example high-assurance application.
The rules for IDF defined in this application note follow the rules defined in the Isolation Design Flow for UltraScale+ FPGAs and Zynq UltraScale+ MPSoCs (XAPP1335).
Download the isolation design example reference files from the Xilinx website. For detailed information about the design files, see Reference Design.
For detailed information about the Isolation Design Flow (IDF), refer to the IDF website.