Revision History - Revision History - XAPP1336

Isolation Design Example for the Zynq UltraScale+ MPSoC (XAPP1336)

Document_ID
XAPP1336
Release_Date
2023-10-20
Revision
2.1 English

The following table shows the revision history for this document.

Section Revision Summary
10/20/2023 Version 2.1
Isolation Design Flow Noted to skip Step 1 of Phase 6 when Vivado 2021.1 and subsequent releases are used.
Vivado Project Creation Updated Figure 5.
04/12/2021 Version 2.0
Figure 1 Added a new figure.
Phase 1 Added steps to generate and build the project along with graphics.
Phase 2 Added more details on net splitting along with graphics.
Phase 3 Added steps for RTL elaboration and to set HD.ISOLATED property along with graphics.
Phase 4 Added steps for demonstrating synthesis along with graphics.
Phase 5 Added steps for further clarity on floorplanning along with graphics.
Phase 6 Added steps for running VIV DRCs along with graphics.
Phase 7 Added steps for implementation along with graphics.
Phase 8 Added steps for VIV placement and routing DRC Run along with graphics.
Conclusion Provided Tcl scripts that allows the user to single-step through the design process.
02/15/2019 Version 1.0
Initial release. N/A