Reference Design - Reference Design

The reference design file contains example Tcl scripts and can be downloaded from the Xilinx website. The following table shows the reference design matrix.

Table 1. Reference Design Matrix
Parameter	Description
General
Developer name	AMD
Target devices	Zynq UltraScale+ devices
Source code provided?	Yes
Source code format (if provided)	Tcl
Design uses code or IP from existing reference design, application note, 3rd party or Vivado software? If yes, list.	N/A
Simulation
Functional simu v2018.3lation performed	N/A
Timing simulation performed?	N/A
Test bench provided for functional and timing simulation?	N/A
Test bench format	N/A
Simulator software and version	N/A
SPICE/IBIS simulations	N/A
Implementation
Synthesis software tools/versions used	Isolation Design Flow (IDF) and Vivado Design Suite 2018.3
Implementation software tool(s) and version	Isolation Design Flow (IDF) and Vivado Design Suite 2018.3
Static timing analysis performed?	N/A
Hardware Verification
Hardware verified?	N/A
Platform used for verification	N/A

Reference Design - Reference Design - XAPP1336

Isolation Design Example for the Zynq UltraScale+ MPSoC (XAPP1336)