Phase 8 - Phase 8 - XAPP1336

Isolation Design Example for the Zynq UltraScale+ MPSoC (XAPP1336)

Document_ID
XAPP1336
Release_Date
2023-10-20
Revision
2.1 English

After implementation completes, use the AMD Vivado™ Isolation Verifier (VIV) 2.0 tool to run a final set of design rule checks to verify both the placement and routing complies with the IDF rules.

Re-run DRC #1 to maintain the provenance in the report, followed by DRC #5 and DRC #6, which are run on the finished design. Refer to Vivado Isolation Verifier User Guide (UG1291) for DRC details.

Follow the steps listed here to execute the VIV DRCs. Alternatively, you can run phase8 Tcl script from Tcl Console by typing source ./lab_phase8.tcl.

  1. Open the Report DRC window by following steps mentioned in Phase 6 and Select Provenance (IDF_VIV2-1) and Implementation (IDF_VIV2-5, IDF_VIV2-6) and click OK.

The result after VIV 2.0 is run is shown in the following figure.

Note: No IDF violations are shown in the DRC Report for this design. Refer to Vivado Isolation Verifier User Guide (UG1291) for DRC detail.