Phase 7 - Phase 7 - XAPP1336

This phase implements the design by:

1. Optimizing the design within the constraints of the AMD isolation design flow (IDF).
2. Placing the design based on the Pblocks.
3. Routing the design.

Run the following command from the Tcl Console to disable buffer insertion for GND and VCC, before running the implementation. The setting of the following parameter is not mandatory for the IDF flow, but it is needed specifically for this lab design.

set_param hd.BufferInsertion false

You need to disable buffer insertion param when ISO module boundary net is connecting to VCC/GND nets. When this param is set to false, no buffers are inserted for VCC/GND nets. If there is a ISO module boundary net which is connected to VCC/GND and the buffer insertion param is enabled, the tools insert buffers and connect VCC/GND nets across the different Isolated boundaries and thus routing fails with Multi Region Net DRC error.

Click Run Implementation under the Implementation menu, on the left of the Vivado GUI. Alternatively, you can run phase7 Tcl script from the Tcl Console by typing source ./lab_phase.7tcl.

Save the project or constraints if asked. If any constraints were modified, the Vivado tool requests starting from Synthesis. When implementation is complete, select the Open Implemented Design option and click OK. The device view pops up and looks like the following figure. If you are asked to close the Synthesized Design before opening the Implemented Design, select Yes. This is a good practice to follow because memory might be limited.

Routing resources view is the default view when opening a routed design. However, it can be turned on and off by selecting the button in the top of the Device View. Refer to Figure 33 for further details. Gaps in the floorplan appear in this view, because the tools do not consider the interconnected tiles associated with all user tiles as part of the Pblock. This is visual only; the gaps do not exist. In this view, you can track a schematic net to the routed net. This is a very powerful view when tracing timing issues.

Also, from this view you can manually route any component or net as you wish. This mode is the Vivado replacement to the ISE FPGA editor. The replacement is significantly more user friendly.

It is possible for routes, not touchdowns, from one isolated region to cross over into another isolated region, if the region in question does not have any routing in that area. This allows for maximum flexibility to the router while still obeying IDF rules for isolation. This only happens in designs where sparsely populated isolated regions are adjacent to regions that are densely populated. No placement or touchdowns are ever allowed outside the intended isolated region. Refer to Isolation Design Flow for UltraScale+ FPGAs and Zynq UltraScale+ MPSoCs (XAPP1335) for details on IDF routing.