Phase 6 - Phase 6 - XAPP1336

Isolation Design Example for the Zynq UltraScale+ MPSoC (XAPP1336)
Document_ID
XAPP1336
Release_Date
2023-10-20
Revision
2.1 English

This phase, as depicted in the following figure, verifies the creation of the fence by checking the Pblock placement, and I/O bank violations caused by incorrect pin assignments.

Vivado Isolation Verifier (VIV) 2.0 is used to run four design rule checks (DRCs) (DRC #1, #2, #3, and #4), as shown in the following figures. Refer to the Vivado Isolation Verifier User Guide (UG1291) for details on the DRCs.

Follow the steps listed here for running the VIV DRCs. Alternatively, you can run phase6 Tcl script from Tcl Console by typing source ./lab_phase6.tcl.

Important: For Vivado versions 2021.1 and later, skip ahead to Step 2 in the following instructions. In these later releases, the VIV DRCs are automatically enabled by the tool when it detects an HD.ISOLATED property set to true.
  1. Enable VIV DRCs by running the following command from the Tcl Console.
    set_param hd.enableIDFDRC true
  2. Open Report DRC… from the Reports window, as shown in the following figure.
  3. Uncheck default under Rule Decks in the Report DRC window. Under Rules, expand Isolation. Check Provenance (IDF_VIV2-1) and Constraints (IDF_VIV2-2, IDF_VIV2-3, IDF_VIV2-4). Click OK to run the DRC.
  4. DRC tab opens after completion. Maximized DRC view looks like the following figure.

The report shows information on the device provenance (IDF_VIV2-1) and the negative results for constraints testing IDF_VIV2-2 I/O bank violation, IDF_VIV2-3 package pin violation, and IDF_VIV2-4 floorplan violation. No IDF violations are shown in the DRC report of this design. Refer to the Vivado Isolation Verifier User Guide (UG1291) for DRC details.